In a Serial Attached SCSI (SAS) communication architecture, a SAS interface engine is provided. The SAS interface engine includes a number of SAS controllers connected to control a peripheral device, e.g., disk drive. Each of the SAS controllers is defined to include a respective sequencer. Each sequencer is defined as a processor chip having a limited memory defined thereon. The sequencers are defined to operate in accordance with sequencer code, i.e., sequencer program instructions. Each sequencer is tasked with controlling delivery of data to or from the device to which it is connected. Additionally, the sequencers can be defined to control other tasks, such as exception handling and status reporting.
As the functionality of the sequencer is expanded, the amount of required sequencer code expands accordingly. The sequencer code can quickly expand beyond the capacity of the limited memory defined onboard the sequencer. Because the sequencer and its associated memory is restricted to a limited amount of chip area, expansion of the functionality of the sequencer causes chip area to become a limiting factor. For example, due to chip area constraints, it may not be feasible to increase the size of the memory onboard the sequencer to accommodate the desired expansion of sequencer functionality.